The present invention relates to a semiconductor design technology; and more particularly, to an internal read signal generator capable of obtaining the margin of setup/hold time of an input signal and a semiconductor memory device having the same.
An internal read signal generated by an external read command is produced in synchronization with a rising of a clock signal. This internal read signal transfers the corresponding read data to an external circuit through an output buffer.
An operation of this internal read signal is changed based on a burst length control of a semiconductor memory device. For example, only the internal read signal which is first generated by a read command is used when the burst length is 4. However, if the burst length is 8, a new internal read signal having further one period of time of the first internal signal is needed. Here, the burst length, as a characteristic of the operations in the synchronous memory device, means the number of successively outputted data when one address signal is inputted.
FIG. 1 is a block diagram illustrating an internal read signal generating circuit for burst length <8>. Referring to FIG. 1, an internal read signal (casprd6d) generating circuit includes two flip-flop circuits (DFFA and DFFB) 101 and 102, a delay circuit (DELAY1) 103 and an output unit 104. More concretely, the internal read signal generating circuit includes: a first inverter INV1 to invert a read CAS (column address strobe) source signal casprd6; a first flip-flop circuit 101 to deliver an output signal of the first inverter (an inverted read CAS source signal casprd6b) in response to the control of CAS clock signal casp4; a second flip-flop circuit 102 to transfer a first output signal DFFAOUTsig of the first flip-flop circuit 101 in response to the control of CAS clock signal casp4; a delay circuit 103 to delay a second output signal DFFBOUTsig of the second flip-flop circuit 102, and a first NAND gate NAND1 of the output unit 104 receiving the output signal of the delay circuit 103 and the inverted read CAS source signal casprd6b from the first inverter INV1.
FIGS. 2a and 2b are timing diagrams of the internal read signal generating circuit of FIG. 1. Referring to FIG. 2, read data RD are read out from a memory in synchronization with a clock signal clk and the read CAS source signal casprd6 is then activated. The first flip-flop 101 delivers the inverted read CAS source signal casprd6b in response to the CAS clock signal casp4, as a control signal, which it produces by delaying a clock signal for a predetermined time. At this time, there is a fixed delay time difference (dt) between the CAS clock signal casp4 and the inverted read CAS source signal casprd6b based on a rising edge of a specific clock signal clk.
The inverted read CAS source signal casprd6b is latched in the first flip-flop circuit 101 at the second rising edge (r1) of the CAS clock signal casp4 so that the inverted read CAS source signal casprd6b which is shifted by a period of one clock signal clk is outputted as the first output signal DFFAOUTsig. Likewise, the second flip-flop circuit 102 shifts the first output signal DFFAOUTsig by a period of one clock signal clk and outputs the shifted signal as the second output signal DFFBOUTsig. Further, the delay circuit 103 adjusts a matching delay value in order that the time difference between the first output signal DFFAOUTsig and the second output signal DFFBOUTsig is 2*tck (tck: a period of clock signal). As a result, the internal read signal casprd6d having burst length <8> is produced.
However, as the operating frequency of the semiconductor memory device gradually moves to a high frequency band, the malfunction of the semiconductor memory device is often caused. Referring to FIG. 2b, when the delay time difference (dt) is greater than a period of time (tck) of the clock signal clk, the first output signal DFFAOUTsig is not produced at the second rising edge (r1) of the CAS clock signal casp4, but produced at the third rising edge (r2). Therefore, the first output signal DFFAOUTsig is not produced and the final output signal, the internal read signal casprd6d, is not normally generated.
As a result, the internal read signal generating circuit of FIG. 1 operated only at the low frequency in which the period of time (tck) of the clock signal clk is bigger than the delay time difference (dt). This acts contrary to the high frequency operation of the semiconductor memory device. Furthermore, the malfunction generated by this kind of the delay time difference (dt) is not limited to the internal read signal generating circuit and it can be generated in other signal generation circuits in which the delay time difference (dt) can be generated.